1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to an in-situ process for fabricating a semiconductor device with integral removal of antireflection and etch stop layers which are separated by an insulator layer.
2. Description of the Related Art
Although the present invention can be applied to the fabrication of a variety of semiconductor devices, a particularly suitable application of the invention relates to the fabrication of a flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) semiconductor memory which includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting select transistors which would enable the cells to be erased independently. All of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block.
Tungsten damascene is a process for fabricating local interconnects which can be advantageously applied to semiconductor devices including flash EEPROMs. The process includes forming an inter level dielectric insulator layer (ILD) of, for example, tetraethylorthosilicate (TEOS) glass over the memory cells, and using Reactive Ion Etching (RIE) to form vertical interconnect holes through the glass down to interconnect areas (source, drain, etc.) of the cells. The holes are filled with tungsten which ohmically contacts the interconnect areas to form the local interconnects.
The TEOS etch is conventionally performed using octaf luorobutene (C4F8) etchant, which also has a high etch rate for silicon. For this reason, a mechanism must be provided for performing the TEOS etch without allowing the etchant to act on the silicon of the underlying interconnect areas.
Such a mechanism includes forming an etch stop layer underneath the TEOS layer, and performing the etch in two stages. The first stage is the octafluorobutene etch through the TEOS layer, which terminates at the etch stop layer since octafluorobutene has a low etch rate for etch stop layer. Suitable materials for the etch stop layer include silicon nitride (Si3N4) and silicon oxynitride (SiON:H).
Then, a second RIE etch is performed using fluoromethane (CH3F), which forms holes through the portions of the etch stop layer that are exposed through the holes in the TEOS layer, down to the interconnect areas of the devices. This is possible because fluoromethane has a high etch rate for silicon nitride, but a low etch rate for TEOS.
The structure can be further facilitated by using a silicide technique to increase the conductivity of the interconnect areas of the cells. Siliciding is a fabrication technique that enables electrical interconnections to be made that have reduced resistance.
The silicide process comprises forming a layer of a refractory metal silicide material such as cobalt, tungsten, titanium, tantalum, molybdenum, etc. on a silicon interconnect area (source or drain diffusion region) or on a polysilicon gate to which ohmic contact is to be made, and then reacting the silicide material with the underlaying silicon material to form a silicide surface layer having much lower resistance than heavily doped silicon or polysilicon. A silicide surface layer formed on a polysilicon gate is called xe2x80x9cpolycidelxe2x80x9d, whereas a silicide surface layer formed on silicon using a self-aligned process is called xe2x80x9csalicidexe2x80x9d.
The holes are precisely formed using photolithography. More specifically, a layer of photoresist is formed over the insulator layer, and exposed to light through a mask which has opaque and transparent areas corresponding to the desired pattern. Light passing through the transparent areas in the mask causes a chemical reaction in the underlying areas of the photoresist such that these areas will be dissolved away when the wafer is exposed to a developing solution.
The result is a photoresist layer having openings therethrough which correspond to the transparent areas of the mask. The patterned photoresist layer is then used as an etch mask such that areas of the insulator layer which are exposed by the openings in the photoresist layer will be selectively removed upon exposure to an appropriate etchant.
With feature sizes of integrated circuits constantly shrinking, photolithographic resolution or definition is becoming increasingly sensitive to reflection during the light exposure step. For this reason, an antireflective coating or layer is preferably provided between the insulator layer and the photoresist layer. Suitable materials for the antireflection layer are silicon oxynitride (SiON:H) and silicon oxime (SiNO:H).
As described above, it is necessary to remove the portions of the etch stop layer overlying the interconnect areas so that ohmic contact can be made between the silicide and the tungsten which fills the holes. In fabricating EEPROMs and certain other devices, it is also necessary to remove the antireflection layer.
This is conventionally done using ex-situ processing involving a number of steps and separate apparatus. First, the etch stop layer overlying the interconnect areas is removed using RIE. Then, the wafer is removed from the RIE chamber, and the photoresist is removed by conventional ashing. Tungsten is formed in the holes to ohmically contact the silicide in the interconnect areas. A chemical-mechanical polishing (CMP) step is performed to remove any tungsten which overlies the antireflection layer. Finally, an oxide buff, which is also a CMP process, is performed to remove the antireflection layer and planarize the upper surface of the structure.
The prior art method of performing these steps is disadvantageous in that it must be performed ex-situ using several types of apparatus, and also in that certain of the steps have undesirable side effects. A notable example is that the oxide buff step for removing the antireflection layer creates non-uniformities in the surface of the underlying insulator layer which must be dealt with in subsequent processing steps.
The present invention overcomes the drawbacks of the prior art by eliminating several process steps and enabling a substantial amount of the fabrication processing to be performed in-situ.
More specifically, a semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) is fabricated by performing a number of process steps in-situ. Semiconductor devices having local interconnect areas are formed on a surface of a semiconductor substrate. An etch stop layer is formed over the surface of the substrate and the devices, and an inter level dielectric layer (ILD) is formed over the etch stop layer. An antireflection layer (ARC) is formed over the insulator layer, and a photoresist layer is formed over the insulator layer.
The photoresist layer is photolithographically patterned to form first holes therethrough which overlie the interconnect areas. Using the patterned photoresist layer as a mask, second holes which underlie the first holes are etched using Reactive Ion Etching (RIE) through the antireflection layer to the insulator layer. Third holes are etched through the insulator layer down to the etch stop layer.
The photoresist layer is removed, and the antireflection layer and portions of the etch stop layer which underlie the third holes are simultaneously removed to form fourth holes through the etch stop layer without adversely affecting the insulator layer and/or the interconnect areas. The third and fourth holes are then filled ex-situ with electrically conductive tungsten which ohmically contacts the interconnect areas to form the local interconnects.
The simultaneous removal of the antireflection layer and the portions of the etch stop layer eliminate several conventional processing steps and enable much of the processing to be performed in-situ.
These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts.